Power supply of the power supply

At the output of the BR1 rectifier, the smoothing tanks of the filter C1, C2 are included. The THR thermistor limits the initial rush of the charging current of these capacitors. The 115V/230V SW switch provides the ability to power the switching power supply from both 220-240V and 110/127V mains.

High-ohm resistors R1, R2, shunt capacitors C1, C2 are symmetrical (equalize voltages on C1 and C2), and also ensure the discharge of these capacitors after the switching power supply is disconnected from the mains. The result of the operation of the input circuits is the appearance on the bus of the rectified voltage of the DC voltage Uep, equal to +310V, with some ripples. 

This switching power supply unit uses a start-up scheme with forced (external) excitation, which is implemented on a special starting transformer T1, on the secondary winding of which, after the power supply is connected to the network, an alternating voltage with the frequency of the supply network appears. This voltage is rectified by diodes D25, D26, which form a two-half-period rectification scheme with a midpoint with the secondary T1. The SZO is the smoothing capacitance of the filter, on which a constant voltage is formed, which is used to power the control chip U4.

The TL494 IC is traditionally used as the control chip in this switching power supply.

The supply voltage from the NWS capacitor is supplied to pin 12 U4. As a result, the output voltage of the internal reference source Uref= -5B appears on pin 14 U4, the internal sawtooth voltage generator of the chip is started, and control voltages appear on pins 8 and 11, which are sequences of square pulses with negative leading edges, shifted relative to each other by half a period. Elements C29, R50 connected to pins 5 and 6 of the U4 chip determine the frequency of the sawtooth voltage generated by the internal generator of the chip.

The matching stage in this switching power supply unit is made according to the non-transversor circuit with separate control. The supply voltage from the NWS capacitor is supplied to the middle points of the primary windings of the control transformers T2, TZ. The output transistors of the U4 ICs act as the transistors of the matching stage and are connected to the OE circuit. The emitters of both transistors (pins 9 and 10 of the chip) are connected to the "package". The collector loads of these transistors are the primary half-windings of the control transformers T2, TZ, connected to pins 8, 11 of the U4 microcircuit (open collectors of the output transistors). Other halves of primary windings T2, TZ with diodes D22 and D23 connected to them form demagnetization circuits of the cores of these transformers.

T2 and TZ transformers control powerful transistors of the half-bridge inverter.

Switching of the output transistors of the microcircuit causes the appearance of pulse control EMF on the secondary windings of control transformers T2, TZ. Under the influence of these EMFs, the power transistors Q1 and Q2 are alternately opened with adjustable pauses ("dead zones"). Therefore, alternating current flows through the primary winding of the T5 power pulse transformer in the form of sawtooth current pulses. This is explained by the fact that the primary winding T5 is included in the diagonal of the electric bridge, one arm of which is formed by transistors Q1, Q2, and the other by capacitors C1, C2. 

When any of the transistors Q1 or Q2 is opened, the primary winding T5 is connected to one of the capacitors C1 or C2, which causes the current to flow through it during the entire time that the transistor is open.

Damper diodes D1, D2 provide the return of energy stored in the scattering inductance of the primary winding T5 during the closed state of transistors Q1, Q2 back to the source (recuperation).

The chain C4, R7, which shunts the primary T5, contributes to the suppression of high-frequency parasitic oscillatory processes that occur in the circuit formed by the inductance of the primary T5 and its inter-turn capacitance, when the transistors Q1 and Q2 are closed, when the current through the primary is abruptly stopped.

The capacitor SZ, connected in series with the primary winding T5, eliminates the direct component of the current through the primary winding T5, thereby eliminating the undesirable magnetization of its core.

Resistors R3, R4 and R5, R6 form the basic dividers for high-power transistors Q1, Q2 respectively and provide an optimal mode of their switching in terms of dynamic power losses on these transistors.

The flow of alternating current through the primary winding T5 causes the presence of alternating square pulse emf on the secondary windings of this transformer.

The T5 power transformer has three secondary windings, each of which has an outlet from the midpoint.

Winding IV provides an output voltage of +5V. Diode assembly SD2 (half-bridge) forms a two-half-period rectification circuit with winding IV with a midpoint (midpoint of winding IV is grounded).

 Elements L2, SW, C11, C12 form a smoothing filter in the +5V channel.

In order to suppress the parasitic high-frequency oscillatory processes that occur during the switching of the diodes of the SD2 assembly, these diodes are shunted with calming RC chains C8, R10nC9, R11.

The diodes of the SD2 assembly are diodes with a Schottky barrier, which achieves the necessary speed and increases the efficiency of the rectifier.

Winding III together with winding IV provides an output voltage of +12V together with a diode assembly (half-bridge) SD1. This assembly forms a two-half-period midpoint straightening pattern with winding III. However, the middle point of winding III is not grounded, but is connected to the +5V output voltage bus. This will make it possible to use Schottky diodes in the +12V generation channel, since the reverse voltage applied to the rectifier diodes is reduced to the permissible level for Schottky diodes.

Elements L1, C6, C7 form a smoothing filter in the +12V channel.

Resistors R9, R12 are designed to accelerate the discharge of the output capacitors of the +5V and +12V buses after the UPS is disconnected from the mains.

RC chain C5, R8 is designed to suppress oscillatory processes occurring in the parasitic circuit formed by the inductance of winding III and its turn-to-turn capacitance.

The I winding with five taps provides negative output voltages of -5V and -12V.

Two discrete diodes D3, D4 form a half-bridge of two-half-period rectification in the -12V generation channel, and D5, D6 diodes in the -5V channel.

Elements L3, C14 and L2, C12 form smoothing filters for these channels.

Winding II, as well as winding III, is shunted with a sedative RC chain R13, C13.

Winding midpoint II is grounded.

Output voltage is stabilized in different ways in different channels.

Negative output voltages of -5V and -12V are stabilized using linear integral three-lead regulators U4 (type 7905) and U2 (type 7912).

For this purpose, the inputs of these stabilizers are supplied with the output voltages of rectifiers from capacitors C14, C15. Output capacitors C16 and C17 produce stabilized output voltages of -12V and -5V.

Diodes D7, D9 ensure discharge of output capacitors C16, C17 through resistors R14, R15 after switching off the switching power supply from the mains. Otherwise, these capacitors would be discharged through the stabilizer circuitry, which is undesirable.

Capacitors R14 and R15 are also discharged through resistors R14 and C15.

Diodes D5 and D10 perform a protective function in case of breakdown of rectifier diodes.

If at least one of these diodes (D3, D4, D5 or D6) turns out to be "punctured", then in the absence of diodes D5, D10, a positive impulse voltage would be applied to the input of the integral stabilizer U1 (or U2), and an alternating current would flow through the electrolytic capacitors C14 or C15, which would lead to their failure.

The presence of diodes D5, D10 in this case eliminates the possibility of such a situation, since the current is closed through them. For example, if the D3 diode is "broken", the positive part of the period when D3 should be closed, the current will be closed in the circuit: k-a D3 - L3 -D7- D5 - "package".

Stabilization of the +5V output voltage is carried out by the PWM method. For this purpose, a measuring resistive divider R51, R52 is connected to the +5V output voltage bus. A signal proportional to the output voltage level in channel +5V is taken from the resistor R51 and fed to the inverting input of the DA3 error amplifier (pin 1 of the control chip). 

The direct input of this amplifier (pin 2) is supplied with a reference voltage level taken from the resistor R48, which is part of the divider VR1, R49, R48, which is connected to the output of the internal reference source of the U4 Uref=+5B chip. As a result, the width (duration) of the control pulses on pins 8 and 11 of the U4 chip is changed in such a way as to return the deviated output voltage of +5V to the nominal value (when the voltage on the +5V bus decreases, the width of the control pulses increases, and when this voltage increases, it decreases).

Stable (without parasitic generation) operation of the entire control loop is ensured by a frequency-dependent negative feedback loop covering the DA3 error amplifier. This chain is enabled between pins 3 and 2 of the control chip U4 (R47, C27).

The +12V output voltage in this UPS is not stabilized.

The output voltage level of this UPS is only adjusted for the +5V and +12V channels, and is controlled by changing the reference voltage level at the direct input of the DA3 error amplifier using the VR1 trim resistor.

If you change the position of the VR1 engine during the UPS setup, the voltage level on the +5V bus, and therefore on the +12V bus, will change within certain limits, since the voltage from the +5V bus is supplied to the middle point of winding III.

The combined protection of this UPS includes: a limiting circuit for controlling the width of control pulses;
a complete short-circuit protection scheme in loads; Incomplete output overvoltage monitoring circuit (+5V bus only).

Let's take a look at each of these schemes. The limiting control circuit uses a current transformer T4 as a sensor, the primary winding of which is connected in series with the primary winding of the power pulse transformer T5.

The resistor R42 is the load of the secondary winding T4, and the diodes D20, D21 form a two-period circuit for rectifying the alternating impulse voltage removed from the load R42.

Resistors R59, R51 form a divider. Part of the voltage is smoothed by a C25 capacitor. The voltage level on this capacitor depends proportionally on the width of the control pulses at the bases of the power transistors Q1, Q2. This level is fed through the R44 resistor to the inverting input of the DA4 error amplifier (pin 15 of the U4 chip). The direct input of this amplifier (pin 16) is grounded. Diodes D20 and D21 are switched on in such a way that the capacitor C25 is charged to negative (relative to the common wire) voltage when current flows through these diodes.

In normal operation, when the width of the control pulses does not exceed the permissible limits, the potential of pin 15 is positive, due to the coupling of this pin through the resistor R45 with the Uref bus. If the width of the control pulses is excessively increased for any reason, the negative voltage at the capacitor C25 increases, and the potential of the pin 15 becomes negative. This results in the output voltage of the error amplifier DA4, which was previously equal to 0V. Further increase in the width of the control pulses leads to the fact that the switching control of the PWM comparator DA2 is transferred to the DA4 amplifier, and the subsequent increase in the width of the control pulses no longer occurs (limitation mode), since the width of these pulses no longer depends on the level of the feedback signal at the direct input of the DA3 error amplifier.

The short-circuit protection scheme in loads can be conditionally divided into the protection of positive voltage generation channels and the protection of negative voltage generation channels, which are implemented in approximately the same way.

The sensor of the short-circuit protection circuit in the loads of positive voltage generation channels (+5V and +12V) is a diode-resistive divider D11, R17 connected between the output buses of these channels. The voltage level at the anode of the D11 diode is a controlled signal. In normal operation, when the voltages on the output buses of the +5V and +12V channels have nominal values, the potential of the diode anode D11 is about +5.8V, because the current flows through the divider-sensor from the +12V bus to the +5V bus through the circuit: +12V bus - R17 - D11 - +56 bus.

The controlled signal from the D11 anode is fed to the resistive divider R18, R19. Part of this voltage is removed from the resistor R19 and fed to the direct input of comparator 1 of the U3 type LM339N chip. The inverting input of this comparator is supplied with a reference voltage level from the resistor R27 of the divider R26, R27, connected to the output of the reference source Uref=+5B of the U4 control chip. The reference level is chosen so that, under normal operation, the forward input potential of comparator 1 is greater than the inverse input potential. Then the output transistor of comparator 1 is closed, and the UPS circuit functions normally in PWM mode.

In the case of a short-circuit in a +12V channel load, for example, the anode potential of diode D11 becomes 0V, so the potential of the inverting input of comparator 1 will become higher than the potential of the direct input, and the output transistor of the comparator will open. This will cause the Q4 transistor to close, which is normally opened by the base current flowing through the circuit: the Upom bus - R39 - R36 - Q4 - "package".

Opening the output transistor of comparator 1 connects the R39 resistor to the "package" and so the Q4 transistor is passively closed by zero offset. Closing the Q4 transistor entails charging the C22 capacitor, which acts as a delay link for the protection response.

The delay is necessary for the reason that in the process of entering the UPS mode, the output voltages on the +5V and +12V buses do not appear immediately, but as the output capacitors of high capacity are charged. On the other hand, the reference voltage from the Uref source appears almost immediately after the UPS is plugged in. Therefore, in start-up mode, comparator 1 switches, its output transistor opens, and if the C22 arresting capacitor was missing, this would trigger the protection immediately when the UPS is plugged in. However, C22 is included in the circuit, and the protection is activated only after the voltage on it reaches the level determined by the ratings of the resistors R37, R58 of the divider connected to the Upom bus and which is the basis for the Q5 transistor. When this happens, the Q5 transistor opens and the R30 resistor is connected through the low internal resistance of this transistor to the "package". Therefore, there is a path for the current of the base of the transistor Q6 to flow through the circuit: Uref - e-6 Q6 - R30 - k-e Q5 - "package".

Transistor Q6 is opened by this current until saturation, as a result of which the voltage Uref=5B, which emitters the transistor Q6, is applied through its low internal resistance to pin 4 of the control chip U4. This, as shown earlier, leads to the shutdown of the digital path of the chip, the loss of output control pulses and the cessation of switching of power transistors Q1, Q2, i.e. to a residual current. A short circuit in the +5V channel load will result in the D11 diode anode anode potential being only about +0.8V. Therefore, the output transistor of the comparator (1) will be opened and a residual current will occur.

Short-circuit protection in the loads of negative voltage generation channels (-5V and -12V) on comparator 2 of the U3 chip is built in a similar way. Elements D12 and R20 form a diode-resistive divider-sensor connected between the output buses of the negative voltage generation channels. The controlled signal is the D12 diode cathode potential. At a short-circuit in a channel load of -5V or -12V, the potential of the D12 cathode increases (from -5.8 to 0V at a short-circuit in a channel load of -12V and up to -0.8V at a short-circuit in a channel load of -5V). In any of these cases, the normally closed output transistor of comparator 2 is opened, which causes the protection to operate according to the above mechanism. In this case, the reference level from the resistor R27 is fed to the direct input of the comparator 2, and the potential of the inverting input is determined by the ratings of the resistors R22, R21. These resistors form a bipolarly powered divider (the R22 resistor is connected to the Uref=+5B bus, and the R21 resistor is connected to the D12 diode cathode, which has a potential of -5.8V in normal UPS operation, as already noted). Therefore, the potential of the inverting input of comparator 2 in normal operation is less than that of the forward input, and the output transistor of the comparator will be closed.

Output surge protection on the +5V bus is implemented on ZD1, D19, R38, C23 elements. The ZD1 Zener Diode (5.1V breakdown) is connected to the +5V output bus, so as long as the voltage on this bus does not exceed +5.1V, the zener diode is closed, and the Q5 transistor is also closed. If the voltage on the +5V bus increases above +5.1V, the zener diode "breaks through", and an unlocking current flows into the base of the transistor Q5, which leads to the opening of the transistor Q6 and the appearance of the voltage Uref=+5B on pin 4 of the control chip U4, i.e. to a residual current. The R38 resistor is the ballast for the ZD1 zener diode. The C23 capacitor prevents the protection from being triggered by accidental short-term voltage spikes on the +5V bus (e.g., as a result of voltage being set after an abrupt decrease in the load current). The D19 diode is decoupling.

The PG signal generation circuitry in this switching power supply is dual-function and is assembled on comparators (3) and (4) of the U3 chip and the Q3 transistor.

The circuit is based on the principle of monitoring the presence of alternating low-frequency voltage on the secondary winding of the starting transformer T1, which operates on this winding only in the presence of a supply voltage on the primary winding T1, i.e. while the switching power supply is connected to the supply network.

Almost immediately after the UPS is connected to the supply network, the auxiliary voltage Upom appears on the NWS capacitor, which feeds the control chip U4 and the auxiliary chip U3. In addition, the AC voltage from the secondary winding of the starting transformer T1 through the diode D13 and the current-limiting resistor R23 charges the capacitor C19. The voltage from C19 is supplied to the resistive divider R24, R25. From the R25 resistor, a portion of this voltage is applied to the direct input of comparator 3, causing its output transistor to close. Immediately after this, the output voltage of the internal reference source of the U4 Uref=+5B chip feeds the divider R26, R27. Therefore, the inverting input of comparator 3 is supplied with a reference level from resistor R27. However, this layer is chosen to be smaller than the level on the direct input, and therefore the output transistor of comparator 3 remains closed. Therefore, the process of charging the retention tank C20 begins along the circuit: Upom - R39 - R30 - C20 - "body".

As the C20 capacitor is charged, the voltage is applied to the inverse input 4 of the U3 chip. The direct input of this comparator is supplied with voltage from the resistor R32 of the divider R31, R32, connected to the Upom bus. As long as the voltage at the charging capacitor C20 does not exceed the voltage at the resistor R32, the output transistor of comparator 4 is closed. Therefore, the opening current flows into the base of the transistor Q3 through the circuit: Upom - R33 - R34 - 6-e Q3 - "package".

The Q3 transistor is open until saturated, and the PG signal taken from its collector is passively low and prevents the processor from starting. During this time, during which the voltage level on the capacitor C20 reaches the level on the resistor R32, the switching power supply has time to reliably enter the rated mode of operation, i.e. all its output voltages appear in full.

As soon as the voltage on C20 exceeds the voltage taken from R32, comparator 4 will switch and its output transistor will open. This will cause the Q3 transistor to close, and the PG signal removed from its R35 collector load becomes active (H-level) and allows the processor to start.

When the switching power supply is switched off from the mains on the secondary winding of the starting transformer T1, the alternating voltage disappears. Therefore, the voltage on the C19 capacitor decreases rapidly due to the small capacitance of the latter (1 μf). As soon as the voltage drop on resistor R25 is less than on resistor R27, comparator 3 will switch and its output transistor will open. This will cause the output voltages of the U4 control chip to be shut down, as the Q4 transistor will be exposed. In addition, through the open output transistor of comparator 3, the process of accelerated discharge of the capacitor C20 will begin in the circuit: (+)C20 - R61 - D14 - k-e of the output transistor of comparator 3 - "package".

As soon as the voltage level on C20 is less than the voltage level on R32, comparator 4 will switch and its output transistor will close. This will cause the Q3 transistor to open and the PG signal go to an inactive low level before the voltages on the UPS output buses begin to decrease unacceptably. This will initialize the system reset signal of the computer and return the entire digital portion of the computer to its original state.

Both comparators 3 and 4 of the PG signal generation circuit are covered by positive feedback using resistors R28 and R60, respectively, which speeds up their switching.

Smooth start-up in this UPS is traditionally ensured by a C24, R41 forming chain connected to pin 4 of the U4 control chip. The residual voltage on pin 4, which determines the maximum possible duration of the output pulses, is specified by the divider R49, R41.

The fan motor is powered by voltage from the capacitor C14 in the voltage generation channel -12V through an additional decoupling L-shaped filter R16, C15.